CPE 201/EE 236 Lab 3

(UNR/2005 Spring)

Logic Expressions and Karnaugh Maps

Introduction (5 points):

As you’ve probably noticed from the reading, there are several ways to minimize complex logical expressions. Karnaugh maps are a visual way of minimizing expressions. Lining the top and left side of the table are the inputs, while inside the table contains the output for any given input combination. The table is set up such that when there are 2 or more 1’s in adjacent cells, the expression that created the table can be reduced.

Example: A’BC’ + AB’C’ + A’BC + AB’C

First, draw the Karnaugh map…

Then circle the adjacent 1’s …

And then you can see that the long expression that you were given can be minimized to just A’B + AB’

Objective (5 points):

The purpose of this lab is to reduce logic functions to their minimized expressions by using Karnaugh Maps. Given a truth table, a logic circuit, or a design specification, a Karnaugh Map is constructed.
From the Karnaugh map a minimized expression is created and used to design a logic circuit.

Procedure (80 points):

In the lab, you might need to work with gates that have more than 2 inputs. For example, you may need a 3-input OR gate. If so, double click on the gate, and in the window that pops up, click on the "Number of Inputs" tab at the top. Then, select the number of inputs you need, and click OK.

Example Problem:

For the given Boolean expression, derive a truth table, draw a Karnaugh map and derive the minimized expression.

A'B'C' + A'B'C + ABC' + AB'C'

Using a Karnaugh map the minimized expression = A'B' + AC'

Using the minimized expression assemble the new circuit and simulate it to verify your results.

The logic converter will generate a truth table and minimized expression of any logic circuit.

0. Important Notice:

From this lab on, draw your own truth tables and write the logic expressions in your lab report, do NOT use the EWB's screen shots for truth tables and logic expressions.

Mark the input ends of the circuits with the corresponding letters (A, B,...) in your K-maps and logical expressions.

Truth tables and K-maps can be drawn with Microsoft Word's "Table". Circles and curves in the K-map can be drawn with Word's AutoShape/drawing.

To activate drawing: Tool-->Customize-->Toolbar-->(check)Drawing.

To draw a circle/ellipse on K-map (nxn table): AutoShapes-->Basic Shapes--->.... (Right-Click on your drawing--->Format AutoShape--->(select No Fill))

Lines/curves can be drawn in the similar way.

Design Specifications (20 points):

For each of the following expressions, derive a truth table, draw a Karnaugh map, and derive the minimized expression.
Using the minimized expression derive the new circuit.
Include the minimized circuit, minimized expression, truth table, and Karnaugh map in your lab report.

A'B'C' + A'B (C' + C) + ABC (10 points).
A'B'C'D' + A'B'CD' + A'B + AB'C'D' + AB'CD' (10 points).

Reverse Engineering (10 points):

For each of the following circuits, determine the truth table, derive the logic expression, and draw a Karnaugh map. Then, minimize the expression, draw the new minimized circuit, and verify your new circuit in EWB.
Include the new minimized circuit, minimized expression, truth table, and Karnaugh map in your lab report.

(10 points)

From the ground up (15 points):

Design the following circuits, and verify your design in EWB.
Include minimized circuit, minimized logical expression, truth table, and Karnaugh map in your lab report.

A 4-input circuit that outputs a 1 ONLY when the input is an even number (2, 4, 6, 8, 10, 12, 14) (10 points).

4. Design and implementation (40 points):

Read IC Chip descriptions and answer the quetion there (5 points).

Design in EWB a 3-input circuit that outputs 1 when the input numbers are 1, 3, and 5. Copy the circuit to your lab report (15 points).

Using K-map, find simplified logic expression (K-map NOT needed in report).

Change the logic expression such that you can use ONLY NAND gates to implement it. Include this expression in your lab reports.

Draw logic circuit in EWB for this expression with 2-input NAND gates. Copy the circuit to your lab reports.

Draw schematic circuit in EWB for this logic express with only one 7400. Copy the circuit to your lab reports.

Implement the circuit on the breadboard and show the result to the TA (using 7400, click here for the 74xxx schematic diagrams) (20 points).