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{\Huge

\fbox{{\bf Segmentation}} 
\bi
\item Memory address access/manipulation is a fundamental processor operation.
\item It must be speeded up as much as possible
\item Registers have very, very fast response times
\item[$\leadsto$] Store Memory addresses in registers as much as possible
\item Problem:
	\be
	\item Registers are 16 bits or 2 bytes 
	\item Memory addresses are 20 bits wide
	\ee
\item Solution:
	\bi
	\item Could use 2 registers, but that  would give us $2^{32}$
addresses; far more than are possible ($2^{20}$)
	\item Intel's address calculation is a little bizarre but very easy to
calculate (for us and for the computer)
	\ei
\ei

\newpage

\fbox{Address Calculation}
\bi
\item Intel does break up the address into two pieces (stored in two registers)
	\be
	\item 	Segment
	\item	Offset
	\ee
\item Rule
	\bi
	\item[] To calculate an address given its {\em segment} and {\em
offset}, multiply the segment by $16_{10}$ and add the offset.
	\ei
\item[] This is the Intel Segmentation Scheme
\item Easy to calculate:
	\be
	\item In binary, simply append 4 zeros to segment and add offset
	\item In Hex, Even more simply, append a single zero and add offset
	\ee
\item In Intels's 8086/80286 Scheme, two 16 bit numbers team up to form a 20
bit address 
\ei

\newpage

\fbox{Examples}
\be
\item $1234:1ABC \rightarrow 12340 + 1ABC = 13DFC$
%\item[]
\item $ABCD:0011 \rightarrow ABCD0 + 0011 = ABCE1$
\item $A79C:4321 \rightarrow A79C0 + 4321 = ABCE1$
%\item[]
\item $FFFF:FFFF \rightarrow FFFF0 + FFFF = 10FFEF$ 
\item[] Too large? $10FFEF - 10000 = 0FFEF$
\ee
\bi
\item Segments are ranges of memory that spread across the 1Mbyte address
space. Maximum length of a segment is 64Kbytes 
	\be
	\item Segment A = 40000 to 4FFFF
	\item Segment B = 7A000 to 82741
	\item Segment C = 1C400 to 28880
	\item Segment D = 17000 to 1FF00
	\item[] Segments C and D overlap
	\item Segment E = 1C400 to 28880
	\item Segments C and E occupy the exact same addresses
	\ee
\ei

\newpage
\fbox{Four Segments that matter}
\bi
\item[] {\bf Paragraphs:} Segment Addresses must be divisible by 16: Last digit
of a segment's 16bit hex address must be 0. That is, Segments must start at
paragraph boundaries. How Conveenient.
\item You only need to worry about 4 segments
\item Those that correspond to the 80x86's segment registers
	\be
	\item CS: the code segment register
	\item DS: the data segment register
	\item SS: the stack segment register
	\item ES: the extra segment register
	\ee
\item During most of this course, we won't even consider what four segments are
in use. The 64K bytes reachable in a single segment is a lot of storage
capacity. typically a program ``sets and forgets'' segment register during
initialization and only works with offsets.
\ei

\newpage

\fbox{The Processor architecture}
\bi
\item Two parts {\LARGE (refer to fig 2.2 in text)}
	\be
	\item The Execution Unit (EU)
	\item The Bus Interface Unit (BIU)
	\ee
\item[EU]: Actual execution of instructions
\item[BIU]: Sending/Receiving information on Data Bus
	\bi
	\item[] A {\bf bus} is just a collection of electrical conductors that
	transmit signals through the machine
	\item[] An 8-bit bus can transmit/receive 8 bits in parallel  (at a
	time) 
	\item All information; code and data, get to the processor thru the BIU
	\item Address Adder: Combines 16-bit segment with 16-bit offset into a
	20 bit address
	\ei
\ei

\newpage


\bi
\item BIU stores code and data in a {\bf Prefetch Queue}
\item If prefetch queue full; BIU must wait for EU to process some
bytes 
\item If prefetch queue empty; EU must wait for BIU to fetch some bytes
\item Address and Data Multiplexing: At different times the signals on these
lines are interpreted as data or addresses
\item[]
\item 4 groups of registers
	\be
	\item 4 Data registers
	\item 4 Index registers
	\item 4 Segment registers
	\item Instruction Pointer and Flags Register
	\ee
\ei

\newpage

\fbox{The registers}
\bi
\item DATA/COMPUTATIONAL Registers: AX, BX, CX, DX
\item These 4 16-bit registers are for general purpose calculations and
storage 
\item ML programs read numbers into these registers from memory,
perform operations on them and write the results back into memory.
\item The low-order 8-bits and high-order 8-bits can be used separately
\item When used as 8-bit storage cells the registers are called
\item[] AH, AL, BH, BL, CH, CL, DH, DL \newline {\LARGE H $\rightarrow$
{\bf H}igh-order byte,  L $\rightarrow$ {\bf L}ow-order byte, esp useful for
working with 1byte ASCII...hint}
\item We can, for example, read a byte from memory into BL, without
affecting the contents of BH.
\ei

\newpage

\bi
\item[AX]: Accumulator, many operations have a shorter (faster) form
that specifies AX implicitly
\item[BX]: Base Register, and can function as an {\bf index} register
	   {\LARGE [BX] $\rightarrow$ implies use contents of BX as an offset}
\item[CX]: Count Register, does certain types of counting automatically
\item[DX]: Data Register, DX stores MSW of 32 bit ops
\item Except for their minor areas of specialization, these 4 registers are
generally interchangeable.
\ei

\newpage

\fbox{The Index group}
\bi
\item SI, DI, BP, SP
\item Special register used for indexing or pointing
\item That is, their contents are usually interpreted as {\em addresses}
\item[SI]: Source Index
\item[DI]: Destination Index
\item[BP]: Base Pointer
\item[SP]: Stack Pointer
\item These registers can also be used for general purpose computation
\item SI and DI are very useful in moving large sequences of bytes around
memory
\ei

\newpage
\fbox{The Segment group: CS, DS, SS, ES }
\bi
\item Special registers used for Intel's addressing scheme
\item Contents interpreted as the segment part of a 20 bit address.
\item {\LARGE Whenever the processor reads/writes memory one of these registers
provides the segment part of the memory address}
\item Each of these registers defines a segment (a 64K block in memory)
\item[CS]: Code Segment, instruction fetches are from the code segment
\item[DS]: Data Segment, data writes/reads are from the data segment
\item[SS]: Stack Segment, determines segment for stack operations
\item[ES]: Extra Segment, freelancer: usually a pointer to an extra data
segment. 
\item These registers {\bf CANNOT} be used for anything else
\ei

\newpage

\fbox{IP and Flags}
\bi
\item[] \fbox{Instruction Pointer (IP)} also called the Program Counter {\bf
always} 
contains the address of the Next Instruction to be Executed.
\item The processor contains logic circuits to adjust IP, so that it always
points to the next instruction.
\item The IP is always interpreted as an {\bf Offset} to the Code Segment (CS)
\ei

\newpage

\bi
\item[] \fbox{Flags Register (FL)} (A flag is an especially noteworthy bit)
\item An oddball register, contains a collection of unrelated boolean facts
\item bit 0 is the Carry flag: {\LARGE signals unsigned overflow}
\item bit 2 is the Parity flag: {\LARGE later...}
\item bit 4 is the Auxiliary flag: {\LARGE later...maybe}
\item bit 6 is the Zero flag: {\LARGE If arithmetic op results in a 0, flag is
set, else reset. Comparisons (subtract two quantities and set flag)}
\item bit 7 is Sign flag: {\LARGE Set if signed arithmetic operation results in
a negative number else reset}
\item bit 8 is Trap flag: {\LARGE later}
\item bit 9 is Interrupt flag: {\LARGE turns interrupts off}
\item bit 10 is Direction flag:{\LARGE String ops direction}
\item bit 11 is Overflow flag:  {\LARGE Set if Signed Overflow, else reset}
\item TVC shows state of each flag
\ei

\newpage

\bi 
\item[] Other Registers that TVC shows in ``big'' mode
\item IR: Instruction register: {\LARGE 1 byte register that holds the current
instruction code to be decoded to figure out what to do}
\item EA: Effective address register: {\LARGE Another 1 byte register also used
in conjunction with IR}
\item X, Y: temporary storage
\item SR, OR, AD: Segment, Offset registers and Address register: {\LARGE SR
always contains the same value as one of the Segment registers, SR * 16 + OR =
AD (20 bits) current 20 bit address in memory.}
\item Z: data latch, processors window to the world. {\LARGE no numbers enter
or leave processor without going thru Z. ZH, ZL are the byte versions, bytes
enter/leave thru ZL, words thru Z}
\item AD, DB: Address and Data Bus: {\LARGE During writes/reads of memory AD
holds address and DB the data to be stored/read from memory at that address}
\ei

\newpage

\fbox{Byte Order in Memory}
\bi
\item Multi-byte data stored with LSbyte at lowest memory address
\item Bytes of increasing significance occupy successively higher addresses
\item example: low mem $\rightarrow$ high mem
	\be
	\item Byte: EB
	\item[] \fbox{E}\fbox{B}
	\item Word: F21C
	\item[] \fbox{1}\fbox{C}\fbox{F}\fbox{2}
	\item Double Word: 1234ABCD
	\item[]\fbox{C}\fbox{D}\fbox{A}\fbox{B}\fbox{3}\fbox{4}\fbox{1}\fbox{2}
	\item An address:  FFFE:1AC2
	\item[]\fbox{C}\fbox{2}\fbox{1}\fbox{A}\fbox{F}\fbox{E}\fbox{F}\fbox{F}
	\ee
\ei



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