CPE 201: Introduction to Computer Engineering

Fall 2007

General Information Course Description Syllabus Assignments/Grading Announcements



Instructor: Monica Nicolescu

E-mail:monica@cs.unr.edu
Office:SEM 239
Phone:(775) 784-1687
Office hours:Tuesday, Thursday: 1-2pm

Teaching assistant: Amol Ambardekar

E-mail:acube3@yahoo.com
Office:323A
Phone:TBA
Office hours:Monday: 5-5:50pm, Wednesday: 1:1:50pm

Time and Place

Lectures: Tuesday, Thursday: 11:00am - 12:15pm, SEM 234
Labs: Monday:6:00 - 9:00pm or Wednesday: 2:00 - 5:00pm or Wednesday 6:00 - 9:00pm

Required Textbook

Digital Design, Fourth Edition, Prentice Hall, 2007.
Authors: Morris Mano, Michael D. Ciletti



Course description

In this course you will learn the fundamentals of number bases binary arithmetic, Boolean logic and logic functions, minimization of logic functions as sums of products, combinational circuits, sequential (state) machines, registers and register transer, counters, memory and programmable logic devices. You will receive hands-on experience in laboratory experiments.

Prerequisites

CS 135 with a "C" or better. (BS-EE students are exempt from the "C" requirement.)



Syllabus

Following are the topics that will be discussed, listed in the approximate order in which they will be covered.
  • Binary Systems (number systems, conversion, binary numbers and arithmetic, Boolean logic)
  • Boolean algebra, DeMorgan theorems, absorption theorem, logic operations, logic functions, logic gates, ICs, minimization needs, minterms
  • Gate & level minimization of 2, 3, 4, and 5 variable logic functions, NAND/NOR gates, HDL acquaintance
  • Combinational logic, analysis and design of arithmetic logic circuits, decoders, encoders, multiplexers, HDL acquaintance
  • Synchronous sequential logic circuits, latches, flip-flops, clocked circuits, HDL examples for sequential circuits, state reduction, design
  • Registers, counters
  • Memory, programmable logic devices, RAM, ROM, PLA, PAL, sequential programmable devices
  • Register transfer level, review

Laboratory

Lab webpage

Class schedule

The topics presented and the lecture notes for each class will gradually be posted below as we cover them in the class. The assignments and their due dates will also be posted in this table. Please check this web page regularly for updates.

Here is a list of errors from the textbook (ignore the errors related to the lecture notes, as those refer to a different instructor.


Date Topic Readings Assignments

Aug 28

Introduction, digital systems, binary numbers Chapter 1: Section 1-1 and lecture notes ---

Aug 30

Number conversions: octal, hexa, complement systems Chapter 1: Sections 1-1 to 1-5 ---

Sep 4

Complement systems, operations with binary numbers Chapter 1: Sections 1-5, 1-6 Hw1 out

Sep 6

Binary codes, storage, registers, binary logic, boolean algebra, basic definitions, axioms Chapter 1: Sections 1-7, 1-8, 1-9 ---

Sep 11

Boolean Algebra, basic definitions, axioms, boolean functions Chapter 2: Sections 2-1 to 2-3 ---

Sep 13

Canonical standard forms Chapter 2: Sections 2-4, 2-5 ---

Sep 18

Canonical standard forms, digital circuit design Chapter 2: Section 2-5 Hw2 out

Sep 20

Gate-level minimization Chapter 2: Sections 2-6, 2-7;
Chapter 3: Sections 3-1, 3-2
---

Sep 25

Homework review --- ---

Sep 27

Invited Lecture: Computer Vision Research --- ---

Oct 2

Gate-level minimization, 2, 3, 4-variable map, don't care conditions Chapter 3: Sections 3-3, 3-4, 3-5, 3-6 Hw3 out
Due date changed to Oct. 23

Oct 4

Products of sums, NAND and NOR gate implementations Chapter 3: Sections 3-6, 3-7 ---

Oct 9

Other 2-level implementations, adders Chapter 3: Sections: 3-8, 3-9
Chapter 4: Sections 4-1, 4-2, 4-3, 4-4
---

Oct 11

Adders, subtractor, decimal adder, binary multiplier Chapter 4: Sections 4-5, 4-6, 4-7 ---

Oct 16

MID-TERM --- ---

Oct 18

Magnitude comparator, decoders, encoders Chapter 4: Sections 4-8, 4-9, 4-10 ---

Oct 23

Multiplexers, Sequential circuits, SR Latche Chapter 4: Section 4-11, Chapter 5: Sections 5-1, 5-2, 5-3 Hw4 out

Oct 25

Flip-Flops (D, T, JK), Characteristic tables Chapter 5: Section 5-4 ---

Oct 30

Homework Review Lecture notes ---

Nov 1

Analysis of sequential circuits, Synthesis of sequential circuits Chapter 5: Section 5-5 ---

Nov 6

Synthesis of sequential circuits Chapter 5: 5-8
Lecture notes
---

Nov 8

State reduction, Synthesis with JK, T flip-flops Chapter 6: Sections 5-7, 5-8 ---

Nov 13

Registers, shift registers, rotate registers, register design Chapter 6: Sections 6-1, 6-2 Hw5 out

Nov 15

Counters Chapter 6: Sections 6-3, 6-4 ---

Nov 20

Counters, memory components: RAM Chapter 6: Section 6-5
Chapter 7: Sections 7-1, 7-2
---

Nov 27

RAM, decoding, error detection and correction, ROM Chapter 7: Sections 7-3, 7-4, 7-5 ---

Nov 29

ROM, PLAs, PAL, sequential devices Chapter 7: Sections 7-5, 7-6, 7-7, 7-8 Hw6 out

Dec 4

Register transfer level design Chapter 8: Sections 8-1, 8-2, 8-4, 8-5 ---

Dec 6

Register transfer level design, classes of digital circuits Chapter 8: Section 8-5, Chapter 2: Section 2-9, Chapter 10: Sections 10-1, 10-2 ---

Dec 11

Review lecture --- ---

Dec 13, 7:30am

Final Exam: comprehensive, with emphasis on material after mid-term --- ---



Assignments and grading

Homework assignments: There will be aproximately 5 homework assignments. The homeworks and their due dates will be posted on the course web page. Homeworks are due on their specified date at the beginning of the class. Some assignments will contain extra-credit problems and some may have a programming component.

Please make sure that you have a CS department computer account - you will need it for the programming assignments. You can obtain a CS department account by filling out the account registration form at the CS department.

Late policy: Each late homework will incur a 10% penalty for each day of delay, but no homework may be submitted later than 3 days after the deadline. Homework is due at the begining of class. No late lab reports will be accepted.

Quizzes: There will be approximately 5 quizzes. The quizzes could be given witout prior announcement.

Academic integrity: Students are encouraged to study together, however each student must individually prepare his/her solutions. Cheating or plagiarism are not permitted and will be sanctioned according with the UNR policy on Academic Standards. You should carefully read the section on Academic Dishonesty found in the UNR Student Handbook (copies of this section are on-line). Your continued enrollment in this course implies that you have read it, and that you subscribe to the principles stated therein.

Exams: there will be one mid-term and one final exam. Both exams will be closed books, closed notes. Permission to take exams on other dates than scheduled will not be given, except for extreme medical emergencies.

Grading policy (tentative, subject to change):
Homework:15%
Labs:15%
Quizzes:15%
Mid-term:25%
Final exam:25%
Attendance and class participation:5%

Grading scheme (tentative, subject to change):
A:90 and above
B:80-89
C:65-79
D:55-64
F:<55




Announcements

Announcements regarding the assignments or other updates will be posted on the class web page and also sent by e-mail. Please check your UNR e-mail account, as this is the address I will use to contact you. If needed, implement e-mail forwarding.
  • The date of the mid-term exam has changed from October 18 to October 16.
  • The due date of homework 3 has moved to October 23.



Created by: Monica NICOLESCU (e-mail:monica@cs.unr.edu)
Last update: 08/13/2007